Consider the keyboard as input device and the steps when the key is pressed are
Microprocessor detects the key change in status of keyboard i.e. the key is pressed.
It receives the encoded information corresponding to pressed key.
It checks the validity of required signal.
Consider the printer as output device
Here microprocessor checks ideal condition of printer, if ideal then sends the data to be printed and required command for that.
For interfacing of typical microprocessor to I/O devices such as keyboard, CRT, printer etc. All need I/O interface circuits which are of mainly two types.
Parallel Interface
The device which can handle data at higher speed cannot support with serial interface. N bits of data are handled simultaneously by the bus and the links to the device directly.
Achieves faster communication but becomes expensive due to need of multiple wires.
Data transfer Modes of Parallel Interfacing
The information exchanged between a microprocessor and an I/O interface circuit consists of input or output data and control information. The status information enable the microprocessor monitor the device and when it is ready then send or receive data. Control information is the command by microprocessor to cause I/O device to take some action. If the device operates at different speeds, then microprocessor can be used to select a particular speed of operation of the device. The techniques used to transfer data between different speed devices and computer is called synchronizing. Different techniques under synchronizing are:1) Simple I/O
For simple I/O, the buffer switch and latch switches i. e. LED are always connected to the input and output ports. The devices are always ready to send or receive data.Here cross line indicate the time for new valid data.
2) Simple strobe I/O)
In many applications, valid data is present on an external device only at a certain time, so it must be read in at that time. E.g. the ASCII-encoded keyboard. When a key is pressed, circuitry on the keyboard sends out the ASCII code for the pressed key on eight parallel data lines, and then sends out a strobe signal on another line to indicate that valid data is present on the eight data lines.
The sending device, such as a keyboard, outputs a parallel data on the data lines, and then outputs an STB signal to let you know that valid data is present.
3) Single Handshaking:
• The peripheral outputs some data and send signal to MP. ―here is the data for you.‖• MP detects asserted signal, reads the data and sends an acknowledge signal (ACK) to indicate data has been read and peripheral can send next data. ―I got that one, send me another.‖
• MP sends or receives data when peripheral is ready.
4) Double Handshaking
• The peripheral asserts its line low to ask MP ―Are you ready?‖• The MP raises its ACK line high to say ― I am ready‖.
• Peripheral then sends data and raises its line low to say ―Here is some valid data for you.‖
• MP then reads the data and drops its ACK line to say, ―I have the data, thank you, and I await your request to send the next byte of data.
Serial Interface /Serial data transmission:
Data are transferred serially one bit at a time starting from Least Significant bit. Slow due to single communication link but inexpensive to implement.
It uses clock to separate consecutive bits.
Its function is to deal with the data on the bus in the parallel mode and communicate with the connected device in serial mode.
Its data bus has n data lines, the serial I/O interface accepts n bit of data simultaneously from the bus and n bits are sent one at a time thus requiring n time slots.
Not suitable for fast operation needed microprocessor.
Serial I/O transfer is more common than the parallel I/O. The two major forms of serial data transmission are:
1. Synchronous serial data transmission:
• Data is transmitted or received based on a clock signal i. e. synchronously.• The transmitting device sends a data bit at each clock pulse.
• Usually one or more SYNC characters are used to indicate the start of each synchronous data stream.
• SYNC characters for each frame of data.
• Transmitting device sends data continuously to the receiving device. If the data is not ready to be transmitted, the transmitter will send SYNC character until the data is available.
• The receiving device waits for data, when it finds the SYNC characters then starts interpreting the data.
2. Asynchronous serial data Transmission:
The receiving device does not need to be synchronized with the transmitting device. Transmitting device send data units when it is ready to send data.
Each data unit must contain start and stop bits for indicating beginning and the end of data unit. And also one parity bit to identify odd or even parity data.
For e.g. to send ASCII character (7 bit)
We need: 1 start bit: beginning of data
1 stop bit: End of data
1 Parity bit: even or odd parity
7 or 8 bit character: actual data transferred
Synchronous vs. Asynchronous Data Transmission
Programmable Peripheral Interface (PPI) - 8255A:
• The INTEL 8255 is a device used to parallel data transfer between processor and slow peripheral devices like ADC, DAC, keyboard, 7-segment display, LCD, etc.
• The 8255 has three ports: Port-A, Port-B and Port-C.
• Port-A can be programmed to work in any one of the three operating modes mode-0, mode-1 and mode-2 as input or output port.
• Port-B can be programmed to work either in mode-0 or mode-1 as input or output port.
• Port-C (8-pins) has different assignments depending on the mode of port-A and port-B.
Fig: Block Diagram of 8255 PPI
• If port-A and B are programmed in mode-0, then the port-C can perform any one of the following functions.
As 8-bit parallel port in mode-0 for input or output.
As two numbers of 4-bit parallel ports in mode-0 for input or output.
The individual pins of port-C can be set or reset for various control applications.
• If port-A is programmed in mode- 1/mode-2 and port-B is programmed in mode-1 then some of the pins of port-C are used for handshake signals and the remaining pins can be used as input/ output lines or individually set/reset for control application.
Key Features of Mode-0,Mode-1 and Mode-2
• Mode 0: Ports A and B operate as either inputs or outputs and Port C is divided into two 4-bit groups either of which can be operated as inputs or outputs• Mode 1: Same as Mode 0 but Port C is used for handshaking and control
• Mode 2: Port A is bidirectional (both input and output) and Port C is used for handshaking. Port B is not used.
The read/write control logic requires six control signals. These signals are given below.
1. RD (low)
: This control signal enables the read operation. When this signal is low, the microprocessor reads data from a selected I/O port of the 8255A.2. WR (low)
: This control signal enables the write operation. When this signal goes low, the microprocessor writes into a selected I/O port or the control register.3. RESET
: This is an active high signal. It clears the control register and set all ports in the input mode.4. CS (low)
, A0 and A1: These are device select signals. They are,8255A OPERATIONAL MODES AND INITIALIZATION
1. MODE 0
• When programmed for MODE 0, the PPI offers three simple I/O ports with no handshaking signals.
• This mode is appropriate for I/O devices that do not need special synchronizing signals to exchange data with the processor.
• A common example is a keyboard used for data entry.
• When used as O/Ps, the PORT c lines can be individually set or reset by sending a special control word to control register address.
• Two halves of PORT C are independent so one half can be initialized as input and the other half as output.
2. MODE 1
• When programmed for MODE 1, the PPI offers PORT A or PORT B for a handshake input/output operation.
• Pins PC0,PC1 and PC2 function as handshake lines for PORT B
• Pins PC3,PC4 and PC5 function as handshake signal for PORT A (input).
• Pins PC6 and PC7 are available for use as input/output lines for PORT A
• If PORT A is initialized as handshake O/P port, then PORT C pins.
• PC3, PC6 and PC7 function as handshake signals.
• PORT C pins PC4 and PC5 are used as input/output lines for PORT A
3. MODE 2
• Only PORT A can be initialized in MODE 2.• In MODE 2, PORT A can be used as bidirectional handshake data transfer.
• This means that data can be outputted / inputted from same eight lines.
• If PORT A is initialized in MODE 2, then pins PC3 through PC7 are used as handshake lines for PORT A.
• The other three pins PC0 through PC2 can be used for I/O port if PORT B is in MODE 0.
• The same 3 pins will be used for PORT B handshake signals if PORT B is initialized in MODE 1.
CONTROL WORDS
MODE SET CONTROL WORD
BIT SET/RESET CONTROL WORD
Programming 8255
Write a program to read the DIP switches and display the reading from port B at port A and from port CL to port CU
Port address: Port A: 8000h (A1 = 0, A0 = 0)
Port B: 8001h (A1 = 0, A0 = 1)
Port C: 8002h (A1 = 1, A0 = 0)
Control Register: 8003h (A1 = 1, A0 = 1)
Program
MVI A, 83H
STA 8003H
LDA 8001H
STA 8000H
LDA 8002H
ANI 0FH
RLC
RLC
RLC
RLC
STA 8002H
HLT
Universal Synchronous Asynchronous Receiver Transmitter (USART) – 8251A
The 8251A is a programmable serial communication interface chip designed for synchronous and asynchronous serial data communication. As a peripheral device of a microcomputer system, it receives parallel data from the CPU and transmits serial data after conversion. This device also receives serial data from the outside and transmits parallel data to the CPU after conversion.
Features of 8251A
• Wide power supply voltage range from 3V to 6V
• Wide temperature range from -40o C to 85o C
• Synchronous communication up to 64 Kbaud
• Asynchronous communication up to 38.4 Kbaud
• Transmitting / Receiving operations under double buffered configuration.
• Error detection capability (Parity, Overrun and Framing)
The functional block diagram of 8251A consists five sections. They are:
• Read/Write control logic
• Transmitter
• Receiver
• Data bus buffer
• Modem control.
Fig: Functional block diagram of 8251A-USART
Read/Write control logic:
• The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register.
• It monitors the data flow.
• This section has three registers and they are control register, status register and data buffer.
• The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with these three registers.
• When C/D(low) is high, the control register is selected for writing control word or reading status word.
• When C/D(low) is low, the data buffer is selected for read/write operation.
• When the reset is high, it forces 8251A into the idle mode.
• The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.
Transmitter section:
• The transmitter section accepts parallel data from CPU and converts them into serial data.
• The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits.
• When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register.
• If buffer register is empty, then TxRDY is goes to high.
• If output register is empty then TxEMPTY goes to high.
• The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART.
• The clock frequency can be 1, 16 or 64 times the baud rate.
Receiver Section:
• The receiver section accepts serial data and converts them into parallel data.• The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.
• When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again.
• If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register.
• The CPU reads the parallel data from the buffer register.
• When the input register loads a parallel data to buffer register, the RxRDY line goes high.
• The clock signal RxC (low) controls the rate at which bits are received by the USART.
• During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission.
During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character
MODEM Control:
• The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines.• This unit takes care of handshake signals for MODEM interface.
Baud rate /Bit rate
The difference between Bit and Baud rate is complicated and intertwining. Both are dependent and inter-related.Bit Rate is how many data bits are transmitted per second.
A baud Rate is the number of times per second a signal in a communications channel changes. Bit rates measure the number of data bits (that is 0′s and 1′s) transmitted in one second in a communication channel. A figure of 2400 bits per second means 2400 zeros or ones can be transmitted in one second, hence the abbreviation bps.
Individual characters (for example letters or numbers) that are also referred to as bytes are composed of several bits.
A baud rate is the number of times a signal in a communications channel changes state or varies. For example, a 2400 baud rate means that the channel can change states up to 2400 times per second. The term ―change state‖ means that it can change from 0 to 1 or from 1 to 0 up to X (in this case, 2400) times per second. It also refers to the actual state of the connection, such as voltage, frequency, or phase level).
The main difference between the two is that one change of state can transmit one bit, or slightly more or less than one bit, that depends on the modulation technique used. So the bit rate (bps) and baud rate (baud per second) have this connection:
If signal is changing every 10/3 ns then,
Baud rate = 1/10/3ns = 3/10*109= 3*108
= 300 MBd
Note:
• If 1 frame of data is coded with 1 bit then band rate and bit rate are same.
• Sometimes frame of data are coded with two of three bits then baud rate and bit rate are not same.
8251 mode register
8251 status register
RS 232C
This interface standard is most widely used standard for serial communication between microcomputers and peripheral devices. The interface, defined by EIA, relates essentially to two types of equipment. The first is known as data terminal equipment, while the second is referred as data communication equipment (DTE). The data terminal equipment (e.g a microcomputer) is capable of sending and/or receiving data via the serial interface. The data communication equipment on the other hand is generally through of as a device which can facilitate serial data communications (e.g modems).• RS 232C works in a negative logic. The standard specifies that ‘the logic one’ level is a voltage between -3 and -15 v and ‘the logic zero’ is a voltage between +3 and +15 V. The commonly used voltages are +12v and -12V.
• The transmission line normally used a twisted pair of shielded wire with a line capacitance of more than 1200PF and no less than 300Pf. The standard specifies the line length to 50 feet only.
• The standard describes the function of 25 signal and handshake pins for serial data transfer. It also specifies that the DTE connector should be male and the DCE connector should be female. Usually 9 pin and 25 pin connectors are available.
The main problem with –RS-232C is that it can only transfer data reliably about 50ft (16.4m) at its maximum rate of 20k band. If longer lines are used the transmission rate has to be drastically reduced. For higher rate of transfers and for longer distance we have another standard defined.
RS 232C interface with DTE and DCE: The figure below shows a interfacing with minimum lines
The signaling in RS-232C is not compatible with the TTL logic level. For TTL 0 v to 0.2V is considered a logic 0 and 3.4 v to 5v as logic 1. But RS-232C works in a negative logic -3 to -15v considered as logic 1 and +3 to +15v as logic 0. Because of this incompatibility of the data lines with the TTL logic, voltage translators called line drivers and line receivers are required to interface TTL logic with RS-232C signals. The line driver MC 1488 converts logic 1 into approx -9V and logic 0 into +9v. Before it is received by the DCE it is again converted by the line receiver MC 1489 into TTL-Compatible logic. The minimum interface required both a computer and a peripheral device requires three lines; pin 2,3 and 7. These lines are defined in relation to the DTE; the terminal transmits on pin 2 and receives as pin 3. On the other hand the DCE transmits on pin 3 and receives on pin 1. Pin 7 is ground pin.
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