• Internal organization of the computer is defined by the sequence of microoperations it performs on data stored in its resisters.
• Every different processor type has its own design (different registers, buses, microoperations, machine instructions, etc)
• Modern processor is a very complex device
• It contains
– Many registers
– Multiple arithmetic units, for both integer and floating point calculations
– The ability to pipeline several consecutive instructions to speed execution
• However, to understand how processors work, we will start with a simplified processor model
• This is similar to what real processors were like ~25 years ago
• M. Morris Mano introduces a simple processor model he calls the Basic Computer.
• We will use this to introduce processor organization and the relationship of the RTL model to the higher level computer processor.
THE BASIC COMPUTER
• The Basic Computer has two components, a processor and memory.• The memory has 4096 words in it
– 4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long
INSTRUCTION CODE AND STORED PROGRAM ORGANIZATION
• Program– A sequence of (machine) instructions
• (Machine) Instruction
– A group of bits that tell the computer to perform a specific operation (a sequence of micro-operation)
• Instruction code is a group of bits that instructs the computer to perform a specific operation.
• It is usually divided into parts. Most basic part is operation (operation code). Operation code is group of bits that defines operations as add, subtract, multiply, shift, complement etc.
• The instructions of a program, along with any needed data are stored in memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates the instruction into the sequence of microoperations necessary to implement it
• Stored program concept is the ability to store and execute instructions.
Stored program concept is the idea that instructions and data are stored together in memory
INSTRUCTION FORMAT
• A computer instruction is often divided into two parts– An opcode (Operation Code) that specifies the operation for that instruction
– An address that specifies the registers and/or locations in memory to use for that operation
• In the Basic Computer, since the memory contains 4096 (= 212) words, we needs 12 bit to specify the memory address that is used by this instruction.
• In the Basic Computer, bit 15 of the instruction specifies the addressing mode (0: direct addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits long, that leaves 3 bits for the instruction’s opcode.
ADDRESSING MODES
• The address field of an instruction can represent either– Direct address: the address in operand field is effective address (the address of the operand), or
– Indirect address: the address in operand field contains the memory address where effective address resides.
• Effective Address (EA)
– The address, where actual data resides is called effective address.
PROCESSOR REGISTERS
• A processor has many registers to hold instructions, addresses, data, etc• The processor has a register, the Program Counter (PC) that holds the memory address of the next instruction to get
– Since the memory in the Basic Computer only has 4096 locations, the PC only needs 12 bits
• In a direct or indirect addressing, the processor needs to keep track of what locations in memory it is addressing: The Address Register (AR) is used for this
– The AR is a 12 bit register in the Basic Computer
• When an operand is found, using either direct or indirect addressing, it is placed in the Data Register (DR).
– The processor then uses this value as data for its operation
• The Basic Computer has a single general purpose register – the Accumulator (AC)
• The significance of a general purpose register is that it can be referred to in instructions
– e.g. load AC with the contents of a specific memory location; store the contents of AC into a specified memory location
• Often a processor will need a scratch register to store intermediate results or other temporary data; in the Basic Computer this is the Temporary Register (TR)
• The Basic Computer uses a very simple model of input/output (I/O) operations
– Input devices are considered to send 8 bits of character data to the processor
– The processor can send 8 bits of character data to output devices
• The Input Register (INPR) holds an 8 bit character got from an input device
• The Output Register (OUTR) holds an 8 bit character to be send to an output device
BASIC COMPUTER REGISTERS
COMMON BUS SYSTEM OF BASIC COMPUTER
• The registers in the Basic Computer are connected using a bus.• This gives a savings in circuitry over complete connections between registers.
• The outputs of seven registers and memory are connected to common bus.
• Three control lines S2, S1, and S0 control which register the bus selects as its input.
• For example, the number along the output of DR is 3.The 16 bits outputs of DR are placed on bus lines when S2S1S0=011.
• Either one of the registers will have its load signal activated, or the memory will have its read signal activated which will determine where the data from the bus gets loaded.
• The particular register whose LD input is enabled, receives data from bus during next clock pulse transition.
• The 12-bit registers, AR and PC, have 0’s loaded onto the bus in the high order 4 bit positions.
• When the 8-bit register OUTR is loaded from the bus, the data comes from the low order 8 bits on the bus.
COMMON BUS SYSTEM
• Three control lines, S2, S1, and S0 control which register the bus selects as its input• Either one of the registers will have its load signal activated, or the memory will have its read signal activated
– Will determine where the data from the bus gets loaded
• The 12-bit registers, AR and PC, have 0’s loaded onto the bus in the high order 4 bit positions
• When the 8-bit register OUTR is loaded from the bus, the data comes from the low order 8 bits on the bus.
• The memory receives the content of bus when its write input is activated.
• The memory places its 16 bit output onto the bus when the read input is activated and S2S1S0 =111.
• The 16 lines of common bus receives information from six registers and the memory unit.
• Five registers have three control input: LD(Load),INR(Increase) and CLR(Clear).
• Two registers have only LD Input.
• The Input data and output data of the memory are connected to common bus but the memory address is connected to AR.
• Therefore AR must always be used to specify a memory address.
• The content of any register can be specified for the memory data input during a write operation.
• Similarly any register can receive the data from memory after a read operation except AC.
• The 16 inputs of AC come from an adder and logic circuit. This circuit has three set of inputs. One set of 16 bit inputs come from the outputs of AC. Another set of 16 bit inputs come from data register(DR).
• The inputs from DR and AC are used for Arithmetic and logic microoperations.
• The result of an addition is transferred to AC and the end carry out of the addition is transferred to flip flop E(Extended AC bit).
• A third set of 8 bit inputs come from the input register INPR.
BASIC COMPUTER INSTRUCTIONS
Basic Computer Instruction Format•The basic computer has 3 instruction code formats. Type of the instruction is recognized by the computer control from 4-bit positions 12 through 15 of the instruction.A computer should have a set of instructions so that the user can construct machine language programs to evaluate any function that is known to be computable.
An Instruction set is said to complete if it contains sufficient Instructions to perform operations in following categories:
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory and the processor register
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT
Instruction set of Basic computer is complete because:
• ADD, CMA (complement), INC can be used to perform addition and subtraction and CIR (circular right shift), CIL (circular left shift) instructions can be used to achieve any kind of shift operations. Addition subtraction and shifting can be used together to achieve multiplication and division. AND, CMA and CLA (clear accumulator) can be used to achieve any logical operations.
• LDA instruction moves data from memory to register and STA instruction moves data from register to memory.
• The branch instructions BUN, BSA and ISZ together with skip instruction provide the mechanism of program control and sequencing.
• INP instruction is used to read data from input device and OUT instruction is used to send data from processor to output device.
CONTROL UNIT
• Control unit (CU) of a processor translates from machine instructions to the control signals for the microoperations that implement them• Control units are implemented in one of two ways
• Hardwired Control
– CU is made up of sequential and combinational circuits to generate the control signals(Control logic is implemented with gates, flipflops, decoders and other digital circuits)
– If logic is changed we need to change the whole circuitry.
– Expensive
– Fast(It can be optimized to produce fast mode of operation)
• Microprogrammed Control
– Control Information is stored in Control memory.
– A control memory on the processor contains microprograms that activate the necessary control signals.
– If logic is changed we only need to change the microprogram.
– cheap
– Slow
• We will consider a hardwired implementation of the control unit for the Basic Computer
TIMING AND CONTROL
Control unit of Basic Computer(Hardwired control unit of Basic computer)The block diagram of hardwired control unit is shown below. It consists of two decoders, a sequence counter and a number of control logic gates.
• An Instruction read from memory is placed in the instruction register(IR) where it is decoded into three parts: I bit, operation code and bits 0 through 11.
• The operation code bits 12 through 14 are decoded with a 3 x 8 decoder producing eight outputs D0 through D7.
• Bit 15 of the instruction is transferred to a flip flop I.
• Bits 0 through 11 are applied to the control logic gates.
• The 4-bit sequence counter can count in binary from 0 through 15.
• The outputs of the counter are decoded into 16 timing signals T0 through T15.
TIMING SIGNALS
- Generated by 4-bit sequence counter and 416 decoder.- The SC can be incremented or cleared.
- Example: T0, T1, T2, T3, T4, T0, T1, . . .
Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC 0
INSTRUCTION CYCLE
• In Basic Computer, a machine instruction is executed in the following cycle:1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect address
4. Execute the instruction
• After an instruction is executed, the cycle starts again at
step 1, for the next instruction
• Note: Every different processor has its own (different) instruction cycle
FETCH and DECODE
The micro operations for fetch and Decode phases can be specified by Following register transfer statements:• Initially the program counter is loaded with the address of the first instruction in the program.
• The Sequence Counter SC is cleared to 0, providing a decoded timing signal T0.
• After each clock pulse is incremented by one, so that the timing signals go through a sequence T0,T1,T2 and so on.
• It is necessary to transfer the address from PC to AR during clock transition associated with the timing signal T0.
• The instruction read from memory is then placed in IR with clock transition associated with the timing signal T1.
• At the same time PC is incremented by one to prepare it for the address of the next instruction in the program.
• At time T2,the operation code in IR is decoded, the indirect bit is transferred to flip flop I, and the address part of the instruction is transferred to AR.
• Note that SC is incremented after each clock pulse to produce the sequence T0,T1 and T2.
• To provide data path for transfer of PC to AR, apply timing signal T0 to achieve following connection:
1. Place content of PC on bus by making S2S1S0 equal to 010.
2. Transfer the content of the bus to AR by enabling the LD input of AR.
DETERMINE THE TYPE OF INSTRUCTION
AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
REGISTER REFERENCE INSTRUCTIONS
Register Reference Instructions are identified when- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3
r = D7 IT3 => Register Reference Instruction
Bi = IR(i) , i=0,1,2,...,11
MEMORY REFERENCE INSTRUCTIONS
- The effective address of the instruction is in AR and was placed there during timing signal T2 when I = 0, or during timing signal T3 when I = 1- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
BSA:
D5T4: M[AR] PC, AR AR + 1
D5T5: PC AR, SC 0
ISZ: Increment and Skip-if-Zero
D6T4: DR M[AR]
D6T5: DR DR + 1
D6T6: M[AR] DR, if (DR = 0) then (PC PC + 1), SC 0
INPUT-OUTPUT AND INTERRUPT
A Terminal with a keyboard and a Printer• Input-Output Configuration
INPR Input register - 8 bits
OUTR Output register - 8 bits
FGI Input flag - 1 bit
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit
- The terminal sends and receives serial information
- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal serially and with the AC in parallel.
- The flags are needed to synchronize the timing difference between I/O device and the computer
PROGRAM CONTROLLED DATA TRANSFER
INPUT-OUTPUT INSTRUCTIONS
D7IT3 = pIR(i) = Bi, i = 6, …, 11
PROGRAM-CONTROLLED INPUT/OUTPUT
- Continuous CPU involvementI/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware
I/O and Interrupt
oThe process of communication just described is referred to as programmed control transfer.
oThe computer keeps checking the flag bit and when it finds it set, it initiates an information transfer.
oThe difference of information flow rate between the computer and that of input output device makes this type of transfer inefficient.
INTERRUPT INITIATED INPUT/OUTPUT
-Open communication only when some data has to be passed --> interrupt.-Interrupts permit other CPU instructions to execute while waiting for I/O to Complete.
- The I/O interface, instead of the CPU, monitors the I/O device.
- When the interface founds that the I/O device is ready for data transfer, it generates an interrupt request to the CPU
- Upon detecting an interrupt, the CPU stops momentarily the task it is doing, branches to the service routine to process the data transfer, and then returns to the task it was performing.
* IEN (Interrupt-enable flip-flop)
- can be set and cleared by instructions
- when cleared, the computer cannot be interrupted
INTERRUPT CYCLE
- The interrupt cycle is a HW implementation of a branch and save return address operation.• Interrupt flip flop R is included in computer.
• When R=0,computer goes through an instruction cycle.
• During the execute phase of instruction cycle, IEN is checked by control.
• If IEN=0,programmer does not want to use interrupt. So, control continues with next instruction cycle.
• If IEN=1,control checks the flag bit.
• If both flags=0, neither the Input nor output register are ready for transfer of Information. In this case control continues with next instruction cycle.
• If both flags=1,flip flop R is set to 1.
• At the end of the execute phase, control checks the value of R and if equal to 1 goes to interrupt cycle instead of instruction cycle.
• Interrupt cycle is hardware implementation of branch and save return address operation.
• Return address available in PC is stored in a specific location where it can be found later when program returns to the Instruction at which it was interrupted.
• Here we choose memory location at address 0 as the place for storing return address.
• Control then inserts address 1 into PC, and clears IEN and R so that no more interruptions can occur until the interrupt request from the flag has been serviced.
DEMONSTRATION OF INTERRUPT CYCLE
Memory - The interrupt cycle is a HW implementation of a branch and save return address operation.- At the beginning of the instruction cycle, the instruction that is read from memory is in address 1.
- At memory address 1, the programmer must store a branch instruction that sends the control to an interrupt service routine
- The instruction that returns the control to the original program is "indirect BUN 0"
REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE
- Interrupt cycle is initiated after the last execute phase if the Interrupt flip flop R=1.- This Flip Flop is set to 1 if IEN=1 and either FGI or FGO is equal to 1.
- This can happen with any clock transition except when Timing Signals T0,T1 or T2 are active.
Interrupt cycle
• During the first timing cycle AR is cleared to 0, and content of PC is transferred to temporary register TR.• During the Second timing signal, the return address is stored in memory at location 0 and PC is cleared to 0.
• The third timing signal increments PC to 1,clears IEN and R and goes back to T0 by clearing SC to 0.
FURTHER QUESTIONS ON INTERRUPT
How can the CPU recognize the device requesting an interrupt ?Since different devices are likely to require different interrupt service routines, how can the CPU obtain the starting address of the appropriate routine in each case ?
Should any device be allowed to interrupt the CPU while another interrupt is being serviced ?
How can the situation be handled when two or more interrupt requests occur simultaneously ?
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